TestSight Developer DFT Analysis determines the characteristics of In-Circuit Tester (ICT) probe contact pad targets. Traditional ICT probe pad types include Test Pads, Vias, and Thru-Hole legs. Bead Probes are a newer alternative contact option and are also included in the analysis.
The DFT Analyzer lists the count and percentage of Nets covered for all pad types for either the Top, Bottom or Both sides of the circuit board. Vias smaller than a specified size can be excluded from the analysis. No connect (NC) and Boundary Scan nets can be included or excluded. In addition, nets that are covered by boundary scan can be excluded or included.
The Test Pad Spacing analysis determines the minimum spacing below a specified amount from all included pad types to any other included pad type. This is used to determine whether the circuit board design has allowed for ICT design requirements.
DFT Analyzer includes a listing of all existing probes as well as the percentage of nets.
The DFT Bead mask analyzer evaluates the bead padstacks (Paste Stencil and Solder Mask layer openings) for accuracy according to Developer’s Bead Design settings. Bead Design utilizes the design rules specified in the Keysight Medalist Bead Probe Handbook.
